1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to using diamond as an etch stop layer during contact formation. The diamond is rendered conductive by incorporating titanium dopants within the diamond using gas cluster ion beam implantation.
2. Description of the Related Art
Fabrication of an integrated circuit involves numerous processing steps. After impurity regions have been placed within a silicon-based substrate and gate areas defined upon the substrate, an interlevel dielectric is formed across the topography to isolate the gate areas and the impurity regions. Interconnect routing is then placed across the semiconductor topography and connected to the impurity regions and/or the gate areas by ohmic contacts formed through the interlevel dielectric. The entire process of making ohmic contacts to the impurity regions and/or the gate areas and routing interconnect material between the ohmic contacts is described generally as "metallization". As the complexity of integrated circuits has increased, the complexity of the metallization composition has also increased. Conductive materials other than metal are commonly used for metallization. As such, the term metallization is generic in its application.
Integrated circuits typically employ active devices known as transistors. A transistor includes a pair of impurity regions, i.e., junctions, laterally separated by a gate conductor which is dielectrically spaced above the substrate within which the junctions reside. The junctions contain a dopant species opposite in type to that of a channel region residing underneath the gate conductor. Formation of an ohmic contact through an interlevel dielectric to a junction involves patterning a protective mask upon areas of the interlevel dielectric exclusive of where the ohmic contact is to be formed. The area of the interlevel dielectric left uncovered by the mask is then etched to form an opening or window directly above the junction to which contact is to be made. The contact window is then filled with a conductive material to form a contact or plug electrically coupled to the junction. Unfortunately, the mask, and hence the contact, may be misaligned with the junction, resulting in increased resistance at the interface between the contact and the junction.
Typically, contact windows are etched through the interlevel dielectric using a dry, plasma etch technique. Unfortunately, it may be difficult to achieve a high etch selectivity ratio of the interlevel dielectric material, e.g., silicon dioxide, relative to the silicon-based junctions. For example, the plasma etch conditions of silicon dioxide ("oxide") must be strictly controlled to ensure that silicon underlying the oxide (SiO.sub.2) is not significantly removed. Otherwise, the depth of the silicon-based junctions may be reduced to the extent that metal subsequently deposited into the contact windows can "spike" entirely through the shallow junctions. As a result of the metal penetrating below the depth of the junctions into the bulk substrate, the junctions may experience large current leakage or even become electrically shorted. These problems may become paramount as junction depth continues to decrease to below 500 .ANG..
A plasma provided with a fluorocarbon, e.g., CF.sub.4, and O.sub.2 may be used to etch oxide, however, Si is etched more rapidly than oxide in a CF.sub.4 --O.sub.2 plasma. While adding H.sub.2 to the CF.sub.4 --O.sub.2 plasma has been found to increase the SiO.sub.2 -to-Si etch rate selectivity, the exact process conditions required to achieve the maximum selectivity ratio varies for different etch reactors. Accordingly, several experimental etch trials must be performed to determine the optimum process conditions necessary to etch oxide at a much faster rate than silicon. Not only are the experimental trials time consuming, they are also costly, and thus add to the costs of an integrated circuit manufacturer.
Incorporating self-aligned, low resistivity silicide structures between the contact windows and the junctions have grown in popularity due to the problems associated with aligning contact windows to the junctions. The presence of the self-aligned suicides, i.e., "salicides" upon the junctions ensures that contact is made to the entire area of each junction. A salicide process involves depositing a refractory metal across the semiconductor topography, and then reacting the metal only in regions where a high concentration of silicon atoms are present. In this manner, salicides (e.g., TiSi.sub.2) may be formed exclusively upon the silicon-based junctions and the upper surface of a polycrystalline silicon ("polysilicon") gate conductor interposed between the junctions. Salicide formed upon polysilicon is generally referred to as "polycide". Regions between the junctions and the sidewall surfaces of the gate conductor may be pre-disposed with dielectric sidewall spacers generally formed from oxide. The sidewall spacers serve to prevent the metal deposited across the semiconductor topography from contacting, and hence reacting with, the polysilicon at the sidewall surfaces of the gate conductor. Absent the sidewall spacers, silicide could form upon the sidewall surfaces of the gate conductor, undesirably shorting the gate conductor to the adjacent junctions.
After salicides have been formed upon the junctions and the gate conductor of a transistor, an interlevel dielectric is deposited across the semiconductor topography. Contact windows are then etched through the interlevel dielectric and filled with a conductive material to form contacts to the salicides. Unfortunately, a high etch selectivity ratio of the interlevel dielectric material, e.g., oxide, relative to salicide may also be extremely difficult to accomplish. Therefore, substantial portions of the salicides may be removed during the overetch time allotted for plasma etching the contact windows. As a result, the resistance to the flow of current between the contacts and the junctions is increased. In the worst case, the entire thickness of the salicides may be etched, completely eliminating the benefits provided by the salicides. Tungsten (W) plugs are often formed within the contact windows using chemical-vapor deposition ("CVD"). The W is typically CVD deposited from a gas comprising SiH.sub.4 and WF.sub.6 or WF.sub.4 at a temperature of 300 to 350.degree. C. W deposition upon TiSi.sub.2 structures may lead to the formation of an interfacial TiF.sub.3 layer between the W and the TiSi.sub.2. The TiF.sub.3 layer undesirably increases the contact resistance between the W and the underlying salicides.
It would therefore be beneficial to devise a process for forming an ohmic contact to a junction of a transistor without being concerned with misalignment and overetch, resulting in undesirably high contact resistance at the junction. It would be beneficial to protect the junction from being etched during the formation of a contact opening through an overlying interlevel dielectric. Otherwise, the junction could become so shallow that conductive material deposited into the contact opening could penetrate entirely through the junction, causing current leakage from the junction. Further, if a salicide resides upon the junction, removal of the salicide must be prevented to ensure that the contact resistance remains as low as possible. Moreover, the W source (i.e., WF.sub.6 or WF.sub.4) used for the CVD deposition of W into the contact opening should be inhibited from contacting TiSi.sub.2 -type salicide, and thus forming TiF.sub.3.